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NXP Semiconductors /MIMXRT1062 /PIT /MCR

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Interpret as MCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FRZ_0)FRZ 0 (MDIS_0)MDIS

FRZ=FRZ_0, MDIS=MDIS_0

Description

PIT Module Control Register

Fields

FRZ

Freeze

0 (FRZ_0): Timers continue to run in Debug mode.

1 (FRZ_1): Timers are stopped in Debug mode.
MDIS

Module Disable - (PIT section)

0 (MDIS_0): Clock for standard PIT timers is enabled.

1 (MDIS_1): Clock for standard PIT timers is disabled.

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data